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CY7C1062AV33
512K x 32 Static RAM
Features
* High speed -- tAA = 8, 10, 12 ns * Low active power -- 1080 mW (max.) * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and CE3 features the address pins (A0 through A18). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip (CE1, CE2, and CE3 LOW) while forcing the Output Enable (OE) LOW and Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when the device is deselected (CE1, CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE1, CE2, and CE3 LOW, and WE LOW). The CY7C1062AV33 is available in a 119-ball pitch ball grid array (PBGA) package. WE CE1 CE2 CE3 OE BA BB BC BD I/O0-I/O31
Functional Description
The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. Writing to the device is accomplished by enabling the chip (CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on
Logic Block Diagram
INPUT BUFFERS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
512K x 32 ARRAY 4096 x 4096
COLUMN DECODER
Selection Guide
-8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com'l Ind'l Com'l/Ind'l 8 300 300 50 -10 10 275 275 50 -12 12 260 260 50 mA Unit ns mA
Cypress Semiconductor Corporation Document #: 38-05137 Rev. *D
A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18
*
3901 North First Street
OUTPUT BUFFERS
SENSE AMPS
*
San Jose, CA 95134 * 408-943-2600 Revised February 21, 2003
CONTROL LOGIC
CY7C1062AV33
Pin Configuration
119-ball PBGA
(Top View)
1 A B C D E F G H J K L M N P R T U
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
2
A A Bc VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
3
A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bd A A
4
A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5
A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bb A A
6
A A Ba VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
7
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DNU I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
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CY7C1062AV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
-8 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX Com'l = 1/tRC Ind'l Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Com'l/Ind'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 300 300 70 2.0 -0.3 -1 -1 Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 2.0 -0.3 -1 -1 -10 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 260 260 70 -12 Min. Max. Unit V V V V A A mA mA mA
ISB2
50
50
50
mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 10 Unit pF pF
AC Test Loads and Waveforms[3]
50 OUTPUT Z0 = 50 VTH = 1.5V 30 pF Including all Components R1 317 of Test Equipment 3.3V 90% GND Rise time > 1 V/ns THEVENIN EQUIVALENT 167 OUTPUT 10% 90% 10% Fall time: > 1 V/ns 1.73V ALL INPUT PULSES
(a)
3.3V Including OUTPUT Jig and Scope
5 pF
(b)
R2 351
(c)
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
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CY7C1062AV33
AC Switching Characteristics Over the Operating Range[4]
-8 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC (typical) to the first access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1, CE2, or CE3 LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z
[6]
-10 Max. Min. 1 10 8 10 3 8 5 10 5 1 5 5 3 5 5 0 8 5 10 5 1 5 5 10 7 7 0 0 7 5.5 0 3 5 5 7 8 12 8 8 0 0 8 6 0 3 1 0 3 1 3 Max.
-12 Min. 1 12 12 12 6 6 6 12 6 6 Max. Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 ns ns
Description
Min. 1 8 3
1 Low-Z[6]
[7]
OE HIGH to High-Z[6] CE1, CE2, or CE3 LOW to 3 0 CE1, CE2, or CE3 HIGH to High-Z[6] CE1, CE2, or CE3 LOW to Power-up Byte Enable to Data Valid Byte Enable to Low-Z[6] Byte Disable to High-Z[6] 8 6 6 0 0 6 5 0 3 6 1 CE1, CE2, or CE3 HIGH to Power-down[7]
Write Cycle[8, 9] Write Cycle Time CE1, CE2, or CE3 LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[6] WE LOW to High-Z[6] Byte Enable to End of Write
Data Retention Waveform
VCC 3.0V tCDR CE
DATA RETENTION MODE VDR > 2V 3.0V tR
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise. 5. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C1062AV33
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS tRC CE1, CE3 CE2 tACE OE tDOE BA, BB, BC, BD tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 10. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
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CY7C1062AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13, 14, 15]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE t BW BA, BB, BC, BD tSD DATAI/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled) [13, 14, 15]
tWC ADDRESS
tSA BA, BB, BC, BD tAW
tBW
tHA tPWE
WE tSCE CE tSD DATAI/O
Notes: 13. CE indicates a combination of all three chip enables. When ACTIVE LOW, CE indicates the CE1, CE2 and CE3 are LOW. 14. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
tHD
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CY7C1062AV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BA, BB, BC, BD tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE1 CE2 CE3 H L L L L L L L L L L L L L H L L L L L L L L L L L H L L L L L L L L L L L L OE X X L L L L L X X X X X H WE X X H H H H H L L L L L H BA X X L L H H H L L H H H X BB X X L H L H H L H L H H X Bc X X L H H L H L H H L H X BD X X L H H H L L H H H L X I/O0- I/O7 High-Z High-Z Data Out Data Out High-Z High-Z High-Z Data In Data In High-Z High-Z High-Z High-Z I/O8- I/O15 High-Z High-Z Data Out High-Z Data Out High-Z High-Z Data In High-Z Data In High-Z High-Z High-Z I/O16- I/O23 High-Z High-Z Data Out High-Z High-Z Data Out High-Z Data In High-Z High-Z Data In High-Z High-Z I/O24- I/O31 High-Z High-Z Data Out High-Z High-Z High-Z Data Out Data In High-Z High-Z High-Z Data In High-Z Mode Power Down Power Down Read All Bits Read Byte A Bits Only Read Byte B Bits Only Read Byte C Bits Only Read Byte D Bits Only Write All Bits Write Byte A Bits Only Write Byte B Bits Only Write Byte C Bits Only Write Byte D Bits Only Selected, Outputs Disabled Power (ISB) (ISB) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC)
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CY7C1062AV33
Ordering Information
Speed (ns) 8 10 12 Ordering Code CY7C1062AV33-8BGC CY7C1062AV33-8BGI CY7C1062AV33-10BGC CY7C1062AV33-10BGI CY7C1062AV33-12BGC CY7C1062AV33-12BGI Package Name BG119 Package Type 14 x 22 mm 119-ball PBGA Operating Range Commercial Industrial Commercial Industrial Commercial Industrial
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1062AV33
Document History Page
Document Title: CY7C1062AV33 512K x 32 Static RAM Document Number: 38-05137 REV. ** *A ECN NO. 109752 117059 Issue Date 02/27/02 09/19/02 Orig. of Change HGK DFP New Data Sheet Removed 15-ns bin and added 8-ns bin. Changed CE2 TO CE2. Changed CIN - input capacitance - from 6 pF to 8 pF. Changed COUT - output capacitance - from 8 pF to 10 pF. Updated ICC, Tsd, and Tdoe parameters. Removed note 7 (IZ/hZ comment). Final Data Sheet. Removed note 2. Added note 3 to "AC Test Loads and Waveforms" and note 7 to tpu and tpd. Changed ISB1 from 100 mA to 70 mA Description of Change
*B *C
119389 120384
10/07/02 11/13/02
DFP DFP
*D
124440
2/25/03
MEG
Document #: 38-05137 Rev. *D
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